This invention relates to a technique of fabricating a semiconductor integrated circuit device and more particularly, to a technique effective for application, for example, to a self-aligned contact (hereinafter referred to simply as SAC) process or a high aspect ratio contact (hereinafter referred to simply as HARC) process in the fabrication method of a semiconductor integrated circuit device.
This type of technique is described, for example, in Japanese Laid-open Patent Application No. Hei 11 (1999)-317392. In this application, there is disclosed a technique wherein when a silicon oxide layer is etched while ensuring great selectivity to a silicon nitride layer, the use of perfluorocycloolefins (containing C5F8) as an etching gas permits a selection ratio to be high and an in-plane variation of the selection ratio to be lowered.
In Japanese Laid-open Patent Application No. Hei 8 (1996)-45917, for example, there is disclosed a technique of high-speed etching of a deep groove or a hole wherein the residence time of a reaction gas in a low pressure condition within a chamber is set at 100 ms or below for etching.